SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 2974 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf
SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 1458 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 1618 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 2136 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 2440 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT  494 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT	0xf
SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT  496 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf
SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT  492 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf