SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 2967 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 1444 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 1604 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 2122 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 2426 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT  487 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT	0x8
SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT  489 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT  485 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8