SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 3443 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10
SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT  937 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT	0x10
SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT  955 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10
SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT  951 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10