SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 3442 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT  936 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT	0x0
SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT  954 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT  950 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0