SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 3149 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x2
SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 1726 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 2252 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 2548 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT  663 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT	0x2
SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT  681 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x3
SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT  677 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x2