SDMA1_STATUS2_REG__CMD_OP__SHIFT 3150 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10
SDMA1_STATUS2_REG__CMD_OP__SHIFT 1728 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10
SDMA1_STATUS2_REG__CMD_OP__SHIFT 2254 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10
SDMA1_STATUS2_REG__CMD_OP__SHIFT 2552 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10
SDMA1_STATUS2_REG__CMD_OP__SHIFT  664 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS2_REG__CMD_OP__SHIFT	0x10
SDMA1_STATUS2_REG__CMD_OP__SHIFT  682 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10
SDMA1_STATUS2_REG__CMD_OP__SHIFT  678 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10