SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 3019 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 1484 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 1648 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 2166 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 2470 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT  539 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT	0x1
SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT  541 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT  537 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1