SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 3018 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 1482 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 1646 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 2164 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 2468 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT  538 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT	0x0
SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT  540 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT  536 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0