SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 3020 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2
SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 1486 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 1650 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 2168 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 2472 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT  540 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT	0x2
SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT  542 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2
SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT  538 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2