SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 3024 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6
SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 1494 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 1658 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 2176 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 2480 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT  544 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT	0x6
SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT  546 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6
SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT  542 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6