SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 5133 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 2573 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 2565 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4