SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 4103 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 1539 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT	0x0
SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 1555 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 1547 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0