SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 4037 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 1662 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 1862 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 2808 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 2922 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 1473 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT	0x0
SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 1487 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 1479 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0