SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 4025 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0
SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 1658 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 1858 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 2804 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 2918 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 1461 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT	0x0
SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 1475 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0
SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 1467 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0