SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 4005 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 1648 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 1848 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 2794 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 2908 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 1443 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT	0x10
SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 1457 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 1449 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10