SDMA1_RLC0_RB_BASE__ADDR__SHIFT 4019 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 SDMA1_RLC0_RB_BASE__ADDR__SHIFT 1654 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 SDMA1_RLC0_RB_BASE__ADDR__SHIFT 1854 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 SDMA1_RLC0_RB_BASE__ADDR__SHIFT 2800 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 SDMA1_RLC0_RB_BASE__ADDR__SHIFT 2914 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 SDMA1_RLC0_RB_BASE__ADDR__SHIFT 1455 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 SDMA1_RLC0_RB_BASE__ADDR__SHIFT 1469 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 SDMA1_RLC0_RB_BASE__ADDR__SHIFT 1461 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0