SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 4157 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 2902 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 3016 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 1591 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT	0x0
SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 1607 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 1599 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0