SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 4082 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 1700 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 1902 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 2848 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 2962 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 1518 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT	0x2
SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 1534 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 1526 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2