SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 1724 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0
SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 1930 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0
SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 2878 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0
SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 2992 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0