SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 3084 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 1538 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 1708 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 2228 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 2532 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
SDMA1_PHASE1_QUANTUM__VALUE__SHIFT  598 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT	0x8
SDMA1_PHASE1_QUANTUM__VALUE__SHIFT  602 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
SDMA1_PHASE1_QUANTUM__VALUE__SHIFT  598 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8