SDMA1_PHASE1_QUANTUM__VALUE_MASK 3087 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
SDMA1_PHASE1_QUANTUM__VALUE_MASK 1537 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00
SDMA1_PHASE1_QUANTUM__VALUE_MASK 1707 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00
SDMA1_PHASE1_QUANTUM__VALUE_MASK 2227 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00
SDMA1_PHASE1_QUANTUM__VALUE_MASK 2531 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00
SDMA1_PHASE1_QUANTUM__VALUE_MASK  601 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_PHASE1_QUANTUM__VALUE_MASK	0x00FFFF00L
SDMA1_PHASE1_QUANTUM__VALUE_MASK  605 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
SDMA1_PHASE1_QUANTUM__VALUE_MASK  601 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L