SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 3077 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 1532 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 1702 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 2222 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 2526 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
SDMA1_PHASE0_QUANTUM__VALUE__SHIFT  591 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT	0x8
SDMA1_PHASE0_QUANTUM__VALUE__SHIFT  595 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
SDMA1_PHASE0_QUANTUM__VALUE__SHIFT  591 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8