SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 3657 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 1574 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 1758 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 2668 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 2788 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 1101 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT	0x4
SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 1111 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 1103 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4