SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 3803 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 2780 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 2894 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 1245 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT	0x4
SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 1257 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 1249 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4