SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 40222 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0
SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT  157 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT	0x0
SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT  157 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0
SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT  157 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0