SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 40209 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa
SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 2552 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 2678 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x7
SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT  144 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT	0xa
SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT  144 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa
SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT  144 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa