SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 40175 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe
SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 2516 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xb
SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 2648 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xb
SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT  109 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT	0xe
SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT  109 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe
SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT  109 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe