SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 2858 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 1384 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 1534 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 2048 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 2352 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT  394 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT	0x2
SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT  396 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT  392 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2