SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT  524 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0x5
SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT  810 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT	0xb
SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT  809 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT  832 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT  826 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb