SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT  523 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x4
SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT  801 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT	0x2
SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT  800 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT  823 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT  817 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2