SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT  815 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT	0x10
SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT  814 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT  837 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT  831 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10