SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT  535 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x10
SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT  819 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT	0x14
SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT  818 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x14
SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT  841 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x14
SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT  835 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x14