SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT  534 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0xf
SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT  818 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT	0x13
SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT  817 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0x13
SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT  840 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0x13
SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT  834 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0x13