SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT  537 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x15
SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT  822 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT	0x19
SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT  821 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x19
SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT  844 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x19
SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT  838 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x19