SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT  538 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x18
SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT  820 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT	0x15
SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT  819 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x15
SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT  842 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x15
SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT  836 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x15