SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT  636 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT  916 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT	0x10
SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT  915 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT  938 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT  932 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10