SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT  769 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT	0x1e
SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT  768 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT                                                            0x1e
SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT  791 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT                                                            0x1e
SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT  785 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT                                                            0x1e