SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT  482 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x15
SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT  767 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT	0x1a
SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT  766 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x1a
SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT  789 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x1a
SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT  783 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x1a