SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT  483 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x18
SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT  768 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT	0x1d
SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT  767 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x1d
SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT  790 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x1d
SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT  784 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x1d