SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT  888 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT	0x0
SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT  887 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT                                                          0x0
SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT  910 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT                                                          0x0
SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT  904 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT                                                          0x0