SDMA0_UCODE_DATA__VALUE__SHIFT 39966 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_UCODE_DATA__VALUE__SHIFT                                                                        0x0
SDMA0_UCODE_DATA__VALUE__SHIFT  838 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
SDMA0_UCODE_DATA__VALUE__SHIFT  910 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
SDMA0_UCODE_DATA__VALUE__SHIFT  914 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
SDMA0_UCODE_DATA__VALUE__SHIFT 1420 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
SDMA0_UCODE_DATA__VALUE__SHIFT   30 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_UCODE_DATA__VALUE__SHIFT	0x0
SDMA0_UCODE_DATA__VALUE__SHIFT   30 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_UCODE_DATA__VALUE__SHIFT                                                                        0x0
SDMA0_UCODE_DATA__VALUE__SHIFT   30 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_UCODE_DATA__VALUE__SHIFT                                                                        0x0
SDMA0_UCODE_DATA__VALUE__SHIFT   30 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_UCODE_DATA__VALUE__SHIFT                                                                        0x0