SDMA0_STATUS_REG__SEM_IDLE__SHIFT  217 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
SDMA0_STATUS_REG__SEM_IDLE__SHIFT  954 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
SDMA0_STATUS_REG__SEM_IDLE__SHIFT 1038 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
SDMA0_STATUS_REG__SEM_IDLE__SHIFT 1056 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
SDMA0_STATUS_REG__SEM_IDLE__SHIFT 1562 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
SDMA0_STATUS_REG__SEM_IDLE__SHIFT  509 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT	0x1a
SDMA0_STATUS_REG__SEM_IDLE__SHIFT  508 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
SDMA0_STATUS_REG__SEM_IDLE__SHIFT  515 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
SDMA0_STATUS_REG__SEM_IDLE__SHIFT  509 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a