SDMA0_STATUS_REG__REG_IDLE__SHIFT  194 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
SDMA0_STATUS_REG__REG_IDLE__SHIFT  912 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
SDMA0_STATUS_REG__REG_IDLE__SHIFT  992 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
SDMA0_STATUS_REG__REG_IDLE__SHIFT 1010 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
SDMA0_STATUS_REG__REG_IDLE__SHIFT 1516 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
SDMA0_STATUS_REG__REG_IDLE__SHIFT  486 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_STATUS_REG__REG_IDLE__SHIFT	0x1
SDMA0_STATUS_REG__REG_IDLE__SHIFT  485 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
SDMA0_STATUS_REG__REG_IDLE__SHIFT  492 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
SDMA0_STATUS_REG__REG_IDLE__SHIFT  486 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1