SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT  210 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT  942 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 1024 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 1042 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 1548 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT  502 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT	0x11
SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT  501 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT  508 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT  502 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11