SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT  206 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT  936 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 1016 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 1034 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 1540 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT  498 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT	0xd
SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT  497 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT  504 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT  498 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd