SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT  215 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT  950 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 1034 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 1052 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 1558 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT  507 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT	0x16
SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT  506 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT  513 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT  507 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16