SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT  212 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT  946 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 1028 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 1046 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 1552 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT  504 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT	0x13
SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT  503 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT  510 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT  504 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13