SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT  199 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT  922 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 1002 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 1020 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 1526 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT  491 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT	0x6
SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT  490 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT  497 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT  491 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6