SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT  201 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT  926 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 1006 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 1024 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 1530 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT  493 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT	0x8
SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT  492 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT  499 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT  493 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8