SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT  712 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT  978 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT	0x0
SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT  977 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 1000 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT  994 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0